1. Field of the Invention
The present invention relates to a multilayer printed wiring board.
2. Description of the Related Art
In recent years, with rapid development of electronic information technology, semiconductor elements are required to have performance more than the conventional performance, and to realize reduction in dimensions and thickness. Followed by this, similar requirements are made for printed wiring boards on which such semiconductor elements are mounted.
However, when the dimensions of the printed wiring board itself are reduced, there exists restriction in the mounting area for mounting, at a high density, semiconductor elements on the surface of the multilayer printed wiring board. In view of the above, in order to solve this problem, there is proposed a multilayer printed wiring board 101 within which a semiconductor element is housed, as shown in FIG. 9 (see Japanese Patent Application Laid-Open Publication No. 2005-39094).
The multilayer printed wiring board 101 includes a first printed wiring board 104 including: a first wiring pattern 102 formed on one side thereof and a second wiring pattern 103 formed on the opposite side thereof, wherein the first and second wiring patterns 102, 103 are electrically conducted to each other; and a semiconductor element 105 included within the multilayer printed wiring board 101 in the state mounted on the second wiring pattern 103.
A first insulating layer 106 is laminated on the second wiring pattern 103, a second insulating layer 107 is laminated on the first insulating layer 106, and a second printed wiring board 108 is laminated on the second insulating layer 107. The second printed wiring board 108 includes a third wiring pattern 109 formed on the surface opposite to the second insulating layer 107, and a fourth wiring pattern 110 formed on the surface opposite to the third wiring pattern 109. The third wiring pattern 109 and the fourth wiring pattern 110 are electrically connected to each other.
In order to form, between the second and third wiring patterns 103 and 109, a space region 111 within which the semiconductor element 105 can be accommodated, the first insulating layer 106 is required to have a thickness d1 larger than that of the semiconductor element 105. As the result of the fact that the first insulating layer 106 includes a first penetration hole 112 penetrated through the inside of the first insulating layer 106 in the thickness direction, and one opening end part of the first penetration hole 112 is closed by the second insulating layer 107, the above-mentioned space region 111 is formed.
On the other hand, the second insulating layer 107 has a predetermined thickness d2, e.g., in order to prevent crosstalk between the semiconductor element 105 and the third wiring pattern 109.
On the third wiring pattern 109, there are formed metallic bumps 113 penetrated through the second insulating layer 107 and the first insulating layer 106 in the thickness direction. The metallic bump 113 allows the third wiring pattern 109 and the second wiring pattern 103 to be electrically conducted to each other.
In the multilayer printed wiring board 101 thus constituted, the semiconductor element 105 is accommodated within the space region 111.
In this case, the metallic bump 113 penetrated through the second insulating layer 107 and the first insulating layer 106 in the thickness direction is formed in a manner as described below.
First, metallic mask having penetration holes at predetermined positions is laminated on the third wiring pattern 109 of the second printed wiring board 108 and a screen-print process of, e.g., silver paste from on the metallic mask to allow all individual materials to have conical shape followed by drying to thereby form metallic bumps 113. At this time, the metallic bump 113 is formed so as to have a height H larger than sum total of the thickness d1 of the first insulating layer 106 and the thickness d2 of the second insulating layer 107.
Next, the second insulating layer 107 having thickness d2 and the first insulating layer 106 having thickness d1 are laminated in order on the third wiring pattern 109 where the metallic bumps 113 are formed. Pressure is applied to the laminated body thus obtained. As a result, the metallic bumps 113 are penetrated through the second insulating layer 107 and the first insulating layer 106 in the thickness direction so that the front end of each metallic bump 113 is exposed from the first insulating layer 106.
Finally, the first printed wiring board 104 is laminated on the first insulating layer 106, from which the front end of each metallic bump 113 is exposed, with the plane surface of the second wiring pattern 103 facing the first insulating layer 106, and is pressure-fitted thereonto. As a result, the first printed wiring board 104 is laminated on the first insulating layer 106. Further, the front end of each metallic bump 113 is collapsed by the second wiring pattern 103. Thus, the third wiring pattern 109 and the second wiring pattern 103 are electrically conducted to each other through the metallic bump 113.
Here, the metallic bump 113 is formed so as to have the following dimensions in order that the metallic bump 113 is penetrated through the second insulating layer 107 and the first insulating layer 106 in the thickness direction. In the case where the thickness d1 of the first insulating layer 106 is, e.g., 120 μm, and the thickness d2 of the second insulating layer 107 is, e.g., 60 μm, the metallic bump 113 is formed so as to take conical shape having height H of, e.g., 400 μm. In this case, the diameter D of the maximum bottom surface is, e.g., 350 μm.
However, when the metallic bump 113 has large diameter D of the maximum bottom surface, e.g., 350 μm, there is an inconvenience such that the metallic bump 113 obstacles high density wiring of the multilayer printed wiring board 101.